1. Field of the Invention
The present invention relates to a data processing unit, and particularly to a data processing unit including a central unit and a peripheral unit operating on separate power supplies.
2. Description of Related Art
FIG. 7 is a block diagram showing a configuration of a conventional data processing unit comprising separate power supplies for its central unit and peripheral unit. In this figure, the reference symbol Vdd designates a power supply for a central unit (called a central use power supply from now on); Vddx designates a power supply for a peripheral unit (called a peripheral use power supply from now on) including a battery;. 100 designates the central unit that includes a CPU and the like and operates on the central use power supply Vdd; 101 designates the peripheral unit that operates on the peripheral use power supply Vddx; 102 designates a data processing unit including the two power supplies, the central use power supply Vdd and the peripheral use power supply Vddx; and each reference numeral 103 designates an input signal to the data processing unit 102.
As the central use power supply Vdd, a stable power supply is used such as a new cell of sufficient capacity. On the other hand, as the peripheral use power supply Vddx, a battery is used which can cause an unexpected power failure (called power down from now on). The power down can arise from an unstable supply voltage due to a battery fault or due to a long time use beyond the lifetime of the battery.
With the foregoing arrangement including the separate power supplies for the central unit and peripheral unit, the conventional data processing unit has a problem in that when the peripheral use power supply Vddx falls into an unexpected power down and its output voltage drops to a low (L) level, the input signals can change their levels from a high (H) to L level, and this can bring about an undesired interrupt if the external interrupt is active at the L level, or cause an unintended signal to enter the central unit.
The present invention is implemented to solve the foregoing problem. It is therefore an object of the present invention to provide a data processing unit capable of preventing a malfunction even if an unstable power supply of a plurality of power supplies causes an unexpected power down.
According to a first aspect of the present invention, there is provide a data processing unit comprising: a first power supply consisting of a stable power supply; a central unit operating on the first power supply; a second power supply; a peripheral unit operating on the second power supply; an interface block for transferring an external input signal to the peripheral unit; and a power-down detector operating on the first power supply and connected to the second power supply, for detecting a power down of the second power supply and for generating a signal informing of the power down when it takes place.
Here, the central unit may comprise a processing block for processing the external input signal supplied through the peripheral unit, and the processing block may disable the external input signal in response to the signal informing of the power down output from the power-down detector.
The central unit may comprise an interrupt handling circuit for executing interrupt processing of the external input signal consisting of an external interrupt signal supplied through the peripheral unit, and the interrupt handling circuit may disable the external interrupt signal in response to the signal informing of the power down output from the power-down detector.
The central unit may comprise a processing block for temporarily storing and holding a data value of the external input signal supplied through the peripheral unit, and the processing block may hold the data value temporarily stored, and disable further input of the external input signal to the processing block in response to the signal informing of the power down output from the power-down detector.
The central unit may comprise a CPU for executing operations, and the CPU may execute an interrupt handler that disables an input of the external input signal in response to the signal informing of the power down output from the power-down detector.
The central unit may include the power-down detector.